Leader of high level programming of reconfigurable accelerators

We provide technical services in the development of novel accelerated applications and porting of ROCCC 2.0 to FPGA platforms. ROCCC 2.0′s powerful tool set is the tool to use for C to VHDL solutions.

The team at JCI has more than 15 years combined experience in compilation of high level languages to FPGA-based hardware accelerators. Our goal is to provide the tools and services needed for our customers to fully take advantage of the untapped parallel nature of reprogrammable hardware.

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Novel way to program accelerators

ROCCC 2.0 is a C to HDL compilation tool focused on FPGA-based code acceleration. Its objectives are to maximize parallelism within the constraints of the target device, optimize clock cycle time by efficient pipelining, and minimize the area utilized.  It also uses extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory to reduce memory latency.

ROCCC 2.0 is the evolution of the original ROCCC project which started at the University of California Riverside.

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