Once a module has been compiled with ROCCC and translated into hardware, you can create a hardware testbench for simulation. For this example, we are going to be using the FIR filter module and generate a testbench for it.
Once it has been compiled, selected “Generate->Testbench” in the ROCCC menu. If you have not yet compiled the module or it cannot be found in the database, the module will need to be recompiled first.
Upon selecting to generate a testbench in the menu, a window will pop up asking for values to be used for the testbench. The table on top will display all of the input ports while the table on bottom will display the output ports. Here we will want to give it sample values to make sure everything is working in our module.
To edit the value for a test set, double click the cell you would like to change. The values that are supported are integer values, floating point values, and hex values. Hex must start with either “x”, “X”, “0x”, or “0X”. The value you put in will be converted to the datatype of the port upon generating the testbench.
You can add multiple test sets to the test bench by pressing the “+” button at the top. This will add new columns to input new values for the testbench. Each time you add a test set, it will copy the values from the previous test set. The maximum allowed test sets are 128. For this example, we are going to use test sets 1 and 2 for testing the correctness of our module.
For test set 3, we are going to intentionally put the expected output value as something that is wrong so you can see what happens in the simulator when an incorrect expected output value is found.
Once you have all the test sets done that you would like to test in the testbench, press “Finish” at the bottom of the window. ROCCC will then generate a VHDL testbench file and place it in the “vhdl” folder for that module.
If you open the testbench file and scroll towards the bottom, you will see the values you placed in the testbench window being put in their respective ports.
With this, we can run our testbench in our simulator.
Testbench Generation for Systems
Once a system has been compiled with ROCCC and translated into hardware, you can create a hardware testbench for simulation. For this example, we are going to be using the FIRSystem system and generate a testbench for it.
Upon selecting “Generate->Testbench” in the ROCCC menu, a window will pop up asking for the testbench values. You will notice that the window looks a little different for system testbenches. For systems, you will have to give test files that have the necessary values to be tested for each stream. If your system has any input or output scalars, ROCCC will ask for them in this window as well.
The stream files must consist of a list of values separated by white space in the order in which they will be read. For FIRsystem, we will simply give it the values 0 to 103 for the input and see if our calculated outputs match. If you put more data than the system requests for a stream, the testbench will only use the first N values it needs. If you do not put enough data in one of these stream files, the testbench may hang waiting to read values during simulation.
Once you have these files made, browse for them in the testbench window and select the correct file for each corresponding stream.
Once you have all the values filled out, select “Finish” at the bottom and the testbench file will be generated for your system in the “vhdl” folder.
For systems, an extra file is needed for running testbenches: StreamHandler.vhdl. This will automatically be placed in the “vhdl” folder when generating a testbench file for a system.
Running the Testbench
Copy all of the necessary vhdl files from the “vhdl” folder to your simulation program and run the simulation. You should then be able to view the waveforms for all of the ports and signals that exist in your component.
If any of your test sets fail, a failure message will be reported in the console of your simulation program.
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